x86 64 - Porting x86_64 Assembly to AArch64 -

i'm trying convert existing inline x86_64 assembly aarch64 compatible version. encountering following errors upon compilation:

/tmp/ccsvqf1i.s:72547: error: operand 1 should integer register -- `str [0x4,x1],#0x43e00000' /tmp/ccsvqf1i.s:72548: error: operand 1 should integer register -- `str [20,x1],2' 

the x86_64 code below if original , aarch64 code attempt @ porting it.

x86_64 assembly:

                __asm__(                         "incq (%0)\n\t"                         "jno  0f\n\t"                         "movl $0x0, (%0)\n\t"                         "movl $0x43e00000, 0x4(%0)\n\t"                         "movb %1, %c2(%0)\n"                         "0:"                         :                         : "r"(&op1->value),                           "n"(is_double),                           "n"(zval_offsetof_type)                         : "cc"); 

aarch64 assembly

                __asm__(                         "add %0, %0, #1\n\t"                         "bvc  0f\n\t"                         "mov %0, #0x0\n\t"                         "str [0x4, %0], #0x43e00000\n\t"                         "str [%c2, %0], %1\n\t"                         "0:"                         :                         : "r"(&op1->value),                           "n"(is_double),                           "n"(zval_offsetof_type)                         : "cc"); 

edit:updated new attempt , error messages

when want can not describe 1 instruction, need split several instructions.

the problem aarch64 doesn't have instruction store immediate value memory. need move immediate value register , store register memory like:

movz    w2, #0x43e0, lsl #16         // move #0x43e00000 register str w2, [x1, #20]                    // store address [x1, #20] orr w2, wzr, #0x2                    // move #0x2 register str w2, [x1, #4]                     // store address [x1, #4] 

arm instructions risc (reduced instruction set computer) instructions. benefit instructions simple , fixed length. x86 has more complicated instructions. still need split behaviour several instructions if hasn't instruction support behavour. can find more information aarch64 in http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0488d/cihggbgb.html.