modelsim - What's wrong with this VHDL code - BCD Counter? -

i'm studying vhdl right now, , have pretty simple homework assignment - need build synchronous bcd counter count 0 9 , when reaches 9, go 0. wanted experiment little decided not code in (at least way see it) traditional way (with if, elseif) when-else statement (mostly due fact counter 0 9 , has go 0 once hits 9).

library ieee;     use ieee.std_logic_1164.all;  entity sync_counter     port (rst, clk: in std_logic); end entity;  architecture implement of sync_counter     signal counter: integer range 0 10; begin         counter <=    0 when (rst = '1') else                       counter + 1 when (clk='1' , clk'event) else                       0 when (counter = 10); end architecture; 

so compiles, in simulation, counter jumps 0 2, after cycle (0-9 - 0) acting normal, meaning counter goes 0 1 should be. same if force rst = '1'.

simulation image:

why jump 0 2 in start?

thank you.

it may not explain why goes 0 2. please post testbench code on front. however, code bad. code translate this, comments:

process(rst, clk, counter) begin     if rst = '1' -- asynchronous reset, far         counter <= 0;     elsif clk'event , clk = '1' -- rising edge, got asynchronous flip-flop?         counter <= counter + 1;     elsif counter = 10 -- this!?! not asynchronous reset, not synchronous reset, not clock. how translate hardware?         counter <= 0;     end if; end process; 

i'm not sure if work in hardware, can't figure out how implemented, want this:

process(rst, clk) begin     if rst = '1' -- asynchronous reset         counter <= 0;     elsif clk'event , clk = '1'         if counter = 9 -- synchronous reset             counter <= 0;         else             counter <= counter + 1;         end if;     end if; end process; 

i leave "when-else" statements purely combinational code, or @ single line reg <= value when rising_edge(clk).